The usefulness of software driven emulators has increased enormously with growth in the complexity of integrated circuits. Basically, an emulation engine operates to mimic the logical design of a set of one or more integrated circuit chips. The emulation of these chips in terms of their logical design is highly desirable for several reasons. The utilization of emulation engines has also grown up with and around the corresponding utilization of design automation tools for the construction and design of integrated circuit chip devices. In particular, as part of the input for the design automation process, logic descriptions of the desired circuit chip functions are provided. The existence of such software tools for processing these descriptions in the design process is well suited to the utilization of emulation engines which are electrically configured to duplicate the same logic function that is provided by a design automation tool.
Utilization of emulation devices permits testing and verification via electrical circuits of logic designs before these designs are committed to a so-called “silicon foundry” for manufacture. The input to such foundries is the functional logic description required for the chip and its output is initially a set of photolithography masks which are then used in the manufacture of the desired electrical circuit chip device. Verifying the logic designs are correct in the early stage of chip manufacturing eliminates the need for costly and time-consuming subsequent passes through a silicon foundry.
Another advantage of emulation systems is that they provide a device that makes possible the early validation of software meant to operate the emulated chips. Thus, software can be designed, evaluated and tested well before the time when actual circuit chips become available. Additionally, emulation systems can also operate as simulator-accelerator devices thus providing a high-speed simulation platform.
Emulation engines of the type contemplated by this invention contain an interconnected array of emulation processors (EP). Each emulation processor (hereinafter also sometimes simply referred to as “processor”) can be programmed to evaluate logic functions (for example, AND, OR XOR, NOT, NOR, NAND, etc.). The program-driven processors operate together as an interconnected unit, emulating the entire desired logic design. However, as integrated circuit designs grow in size, more emulation processors are required to accomplish the emulation task. An aim, therefore, is to increase the capacity of emulation engines in order to meet the increasingly difficult task of emulating more and more complex circuits and logic functions by increasing the number of emulation processors in each of its modules.
For purposes of better understanding the structure and operation of emulation devices generally, and this invention particularly, U.S. Pat. No. 5,551,013 and patent application Ser. No. 09/373,125 filed Aug. 12, 1999, both of which are assigned to the assignee of this application, are hereby incorporated herein by reference. The teachings of the pending application improve the basic design of the U.S. Pat. No. 5,551,013 patent by interconnecting processors into clusters.
U.S. Pat. No. 5,551,013, shows an emulation module having multiple (e.g. 64) processors. Multiple modules are mounted on printed circuit boards, and the boards are interconnected by cables. All processors within the module are identical. The sequencer and the interconnection network occurs only once in a module. The control stores hold a program created by an emulation compiler for a specified processor and the stacks hold data and inputs previously generated, which are addressed by fields in a corresponding control word to locate the bits for input to the logic element. During each step of the sequencer, an emulation processor emulates a logic function according to the emulation program. A data flow control interprets the current control word to route and latch data within the processor. The node-bit-out signal from a specified processor is presented to the interconnection network where it is distributed to each of the multiplexers (one for each processor) of the module. The node address field in the control word allows a specified processor to select for its node-bit-in signal the node-bit-out signal from any of the processors within its module. The node bit is stored in the input stack on every step. During any operation the node-bit-out signal of a specified processor may be accessed by none, one, or all of the processors within the module.
A bus connected to the processor output multiplexers enables an output from any emulation processor to be transferred to an input of any other of the emulation processors. As explained in the copending application Ser. No. 10/373,125, now U.S. Pat. No. 6,618,698, clusters of processors are advantageously interconnected as an emulation engine such that the setup and storing of results is done in parallel, while the output of one evaluation unit is made available as the input of the next evaluation unit. For this purpose, processors share input and data stacks, and have a set of ‘cascade’ connections which provides access to the intermediate values. By tapping ‘intermediate’ values from one processor, and feeding them to the next, significant emulation speedup is achieved.
At the operating speeds contemplated for the next generation emulator processor chip (ET4), a signal traveling in an interconnecting cable between two printed circuit boards experiences a propagation delay that must be accounted for in the operation of the system. A number of conductors (e.g. 64) are bundled into each cable, with all conductors in a given cable the same length. Each conductor in the cable is connected at one end to the pin or terminal of an input connector and at its other end to a pin or output terminal. The corresponding input and output pins are identified in a sequential order (e.g. input pin 0 is connected to output pin 0, input pin 1 to output pin 1, and so on). In general, a short cable is desirable because the propagation delay is a function of the cable length. However, because of the physical separation of the various boards that must be interconnected, it is advantageous to use cables of more than one length; shorter cables where possible and longer cables where necessary. While the propagation delay for a given cable length is known, in a completely assembled emulator engine, the user can not readily determine the length of the cable that has been used. While there have been proposals in the prior art for determining cable lengths in situ, these prior art methods are inefficient.